(1) Field of the Invention
The present invention relates to a CAD (computer aided design) technique used in layout design of a printed circuit board (hereinafter called a “PCB”), and in particular to a technique for checking whether the layout of a PCB defined according to layout data created using a CAD system will enable bypass capacitors positioned on the PCB to function effectively.
(2) Description of the Related Art
In recent years, high performance and digitalization of electronic devices has lead to the use of high-speed digital ICs (hereinafter called “high-speed IC(s)”) as main structural components of such electrical devices.
A high-speed IC performs high-speed switching operations which cause high frequency fluctuations in the power source voltage and parasitic noise emission. For this reason, bypass capacitors are generally placed on the PCB on which a high-speed IC is mounted, positioned near the power pins of the high-speed IC.
Appropriate positioning of bypass capacitors stabilizes high frequency fluctuations caused in the voltage by high-speed switching, by supplementing with charge stored in the bypass capacitor, and also feeding high frequency components back to a GND pin of the high-speed IC so that parasite noise is confined to the area around the high-speed IC.
Positioning of components and wiring patterns to be mounted on a PCB is generally determined by a designer who using a CAD system. However, mistakes can occur in the positioning that prevent by pass capacitors from functioning effectively.
One technique for checking for mistakes in the layout is a “Wiring Structure Check System for Printed Board” (hereinafter simply called a “check system”) disclosed in Japanese Laid-Open. Patent Application No. 2002-16337.
The check system determines that an error exists in wiring structure provisionally designed on a, PCB when the wiring structure fulfills one of several predetermined error conditions, such as conditions according to which the bypass capacitors will not function effectively. When an error exists, the check system displays an instruction regarding a measure that can be taken in relation to the error (hereinafter called an “error measure instruction”).
Examples of cases in which the check system displays an error measure instruction are when a bypass capacitor is positioned corresponding to more than a predetermined number of high-speed IC power pins, and when a via exists on the wiring path between a bypass capacitor and a high-speed IC power pin.
However, there are a number of error conditions for which the above-described check system in unable to check.
One example is when a power via exists at a position that is on a wiring path connected to the power pin, but that is not on the path between the bypass capacitor and the high-speed IC power pin. The bypass capacitor will not function effectively in such a case.
In order for a bypass capacitor to function effectively, it is necessary for the impedance of the path between the power pin and the bypass capacitor to be lower than the impedance of the path between the power pin and the power source, so that the high-frequency current flows towards the bypass capacitor. However, if the wiring distance between the power via and the power pin is shorter than the wiring distance between the power pin and the bypass capacitor, the impedance between the power pin and the power source will be lower than the impedance between the power pin and the bypass capacitor, and the bypass capacitor may be unable to function effectively.
Since the above-described check system does not check whether a via exists on the wiring path between the bypass capacitor and the power pin of the high-speed IC, it is unable to check for this kind of error condition.
Furthermore, the check system displays an error measure instruction when a via exists on the path of a power pattern to which the bypass capacitor and the power pin of the high-speed IC are connected, even though this is not necessarily an error.
Although it would not be a problem for an error to be detected if a via is always connected to a power plane, if the via is connected not to a power plane but to a power pattern of the wiring, the impedance of the wiring between the via and the power source of the power pattern must be taken into consideration. In such a case, the impedance between the power pin and the power source is higher than the impedance between the power pin and the bypass capacitor, and therefore it is mistaken to always judge that an error exists.